Data transfer between a data transmitter and a data receiver entail problems associated with proper timing of data arrival at the receiver input. In some applications, the received data may be misaligned with the clock signal, so that the data timing is skewed, which may result in incorrect data being sampled by the receiver. The problem may be inherent in the system, such as when trace length on the board are not of uniform length for the input lines and the clock signal. In other instances, the skew between the data and clock timing may be designed into a specification as a permitted tolerance, so that the designer may need to adjust for the skew at the receiver end.
The System Packet Interface Level 4 (SPI-4) protocol specification allows for some skew between the various data and clock pairs. Although this loose tolerance reduces the system complexity, each SPI-4 receiver is required to implement some deskew logic to recover the timing. A variety of deskew techniques may be implemented and some implementations achieve the deskew by some sort of averaging algorithm at the pad level.
The described embodiments of the invention address the deskew of SPI-4 interface, as well as other data transfer interfaces.